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Codex dc1df325cb dita_v2: port M5 native-artifact provenance UP to canonical upstream

M5 (native_artifact.py + rust_backend build_verified_artifact/verify_artifact hooks)
existed ONLY in the uv/exec-refactor worktree. Canonical never received it, so
vendor_sync.sh downgraded the vendored copy back to a raw 'cargo build' — the same
mechanism by which M1's relock clobbered the bingx_venue telemetry fix and orphaned
6 live positions. Canonical is the source of truth; M5 belongs here.

Co-Authored-By: Claude Opus 4.8 <noreply@anthropic.com>

2026-07-13 05:28:05 +02:00

hzbridge/src

M5: implement real Iceoryx2Sink — iceoryx2 0.9.1 production plane sink

2026-06-16 21:08:16 +02:00

MALKHUT

malkhut(fix): wire workers into CMA training loop

2026-07-13 03:25:55 +02:00

Observability

PINK: TUI Hz fix + DC gate + ACB boost + 10 new tests (104/104 green)

2026-06-03 14:00:48 +02:00

prod

dita_v2: port M5 native-artifact provenance UP to canonical upstream