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Codex 82eb5f551a exec(uv): wire T1 smart-exec into PRIME runner (gated UV_SMART_EXEC, lazy)

Bolts SmartExecBridge into the flight's scan loop behind UV_SMART_EXEC (default off). Fully
lazy: flag off => smart_bridge is never imported and the naive maybe_promote runs unchanged
(verified: runner import does not load smart_bridge when the flag is unset). Flag on =>
entries rest as PostOnly GTX makers, exits stay MARKET, the 6s tick drives TTL-abandon.
Reuses bridge.gate (two-man rule) + bridge.stats. runner.py compiles; wire import-safe both
paths. This is the 'bolt to flight 5/6' — dormant until an operator flips the flag and restarts.

Co-Authored-By: Claude Opus 4.8 <noreply@anthropic.com>

2026-07-15 09:37:15 +02:00

.claude/skills/h6i-irc

tools(h6i): wire mode — stateless send/catchup/listen supersede resident client (zombied in prod; server holds state)

2026-07-14 17:51:47 +02:00

hzbridge/src

M5: implement real Iceoryx2Sink — iceoryx2 0.9.1 production plane sink

2026-06-16 21:08:16 +02:00

MALKHUT

malkhut(e2e): CMA-ES disabled for pure 100-opponent episode loop

2026-07-15 00:48:48 +02:00

Observability

PINK: TUI Hz fix + DC gate + ACB boost + 10 new tests (104/104 green)