3d7b00e28d
First commit of the previously-untracked PINK-on-DITAv2 migration system (execution moves to the Rust kernel; policy stays on legacy DITA, so Alpha Engine algorithmic integrity is preserved). BLUE is untouched. Sprint 0 (safety snapshot + flaw-fix verification, MARKET single-leg scope): - Verified Rust FSM fixes (flaws 2,4,10,11,13) by source read of lib.rs. - Hardened 5 vacuous/guarded assertions in test_flaws.py so each flaw test genuinely exercises its fix. Most important: Flaw 5 now asserts capital moves by EXACTLY realized PnL (was entering/exiting at the same price). - Offline suites: 533 passed, 0 failed (35 flaws + 402 kernel/accounting/ bridge + 96 runtime/persistence/multi-exit/restart/seams). - GATE PASS: MARKET-path-critical flaws 1,2,5 confirmed fixed + green. - Added SPRINT0_FLAW_VERIFICATION.md report and _rust_kernel/.gitignore (excludes Rust target/ build artifacts). LIMIT/partial-fill remain explicitly out of scope (MARKET-only bring-up). Co-Authored-By: Claude Opus 4.8 <noreply@anthropic.com>
95 lines
3.4 KiB
Python
95 lines
3.4 KiB
Python
from __future__ import annotations
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from uuid import uuid4
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import os
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import unittest
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from prod.clean_arch.dita_v2 import (
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BackendMode,
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ControlUpdate,
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InMemoryControlPlane,
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ZincControlPlane,
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KernelControlSnapshot,
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KernelMode,
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KernelVerbosity,
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RealZincControlPlane,
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build_control_plane,
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)
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from prod.clean_arch.dita_v2.real_control_plane import SharedRegion
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HAS_REAL_ZINC = SharedRegion is not None
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@unittest.skipUnless(HAS_REAL_ZINC, "Real Zinc adapter is unavailable")
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class TestDITAv2RealControlPlane(unittest.TestCase):
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def test_build_control_plane_defaults_to_zinc(self) -> None:
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plane = build_control_plane()
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self.assertIsInstance(plane, ZincControlPlane)
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def test_roundtrip_update_and_read(self) -> None:
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prefix = f"dita_v2_control_{uuid4().hex}"
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writer = RealZincControlPlane(prefix=prefix, create=True)
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reader = RealZincControlPlane(prefix=prefix, create=False)
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try:
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snapshot = writer.update(
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ControlUpdate(
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mode=KernelMode.DEBUG,
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verbosity=KernelVerbosity.TRACE,
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backend_mode=BackendMode.BINGX,
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trace_transitions=True,
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mirror_to_hazelcast=True,
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)
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)
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self.assertEqual(snapshot.mode, KernelMode.DEBUG)
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self.assertEqual(snapshot.verbosity, KernelVerbosity.TRACE)
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self.assertEqual(snapshot.backend_mode, BackendMode.BINGX)
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self.assertTrue(snapshot.trace_transitions)
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read_back = reader.read()
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self.assertEqual(read_back.mode, KernelMode.DEBUG)
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self.assertEqual(read_back.verbosity, KernelVerbosity.TRACE)
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self.assertEqual(read_back.backend_mode, BackendMode.BINGX)
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self.assertTrue(read_back.trace_transitions)
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finally:
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writer.close()
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reader.close()
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def test_env_can_select_real_control_plane(self) -> None:
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prefix = f"dita_v2_control_{uuid4().hex}"
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previous = os.environ.get("DITA_V2_CONTROL_PLANE")
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os.environ["DITA_V2_CONTROL_PLANE"] = "REAL_ZINC"
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try:
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plane = build_control_plane(prefix=prefix)
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self.assertIsInstance(plane, RealZincControlPlane)
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if isinstance(plane, RealZincControlPlane):
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plane.close()
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finally:
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if previous is None:
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os.environ.pop("DITA_V2_CONTROL_PLANE", None)
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else:
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os.environ["DITA_V2_CONTROL_PLANE"] = previous
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def test_initial_snapshot_is_default(self) -> None:
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prefix = f"dita_v2_control_{uuid4().hex}"
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plane = RealZincControlPlane(prefix=prefix, create=True)
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try:
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snapshot = plane.read()
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self.assertEqual(snapshot, KernelControlSnapshot())
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finally:
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plane.close()
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class TestDITAv2InMemoryControlPlane(unittest.TestCase):
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def test_wait_and_notify(self) -> None:
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plane = InMemoryControlPlane()
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self.assertFalse(plane.wait(timeout_ms=1))
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plane.notify()
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self.assertTrue(plane.wait(timeout_ms=1))
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snapshot = plane.update(ControlUpdate(mode=KernelMode.DEBUG, verbosity=KernelVerbosity.TRACE))
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self.assertEqual(snapshot.mode, KernelMode.DEBUG)
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self.assertEqual(snapshot.verbosity, KernelVerbosity.TRACE)
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if __name__ == "__main__":
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unittest.main()
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