3d7b00e28d
First commit of the previously-untracked PINK-on-DITAv2 migration system (execution moves to the Rust kernel; policy stays on legacy DITA, so Alpha Engine algorithmic integrity is preserved). BLUE is untouched. Sprint 0 (safety snapshot + flaw-fix verification, MARKET single-leg scope): - Verified Rust FSM fixes (flaws 2,4,10,11,13) by source read of lib.rs. - Hardened 5 vacuous/guarded assertions in test_flaws.py so each flaw test genuinely exercises its fix. Most important: Flaw 5 now asserts capital moves by EXACTLY realized PnL (was entering/exiting at the same price). - Offline suites: 533 passed, 0 failed (35 flaws + 402 kernel/accounting/ bridge + 96 runtime/persistence/multi-exit/restart/seams). - GATE PASS: MARKET-path-critical flaws 1,2,5 confirmed fixed + green. - Added SPRINT0_FLAW_VERIFICATION.md report and _rust_kernel/.gitignore (excludes Rust target/ build artifacts). LIMIT/partial-fill remain explicitly out of scope (MARKET-only bring-up). Co-Authored-By: Claude Opus 4.8 <noreply@anthropic.com>
136 lines
4.6 KiB
Python
136 lines
4.6 KiB
Python
"""Python prototype of the Zinc hot-path plane.
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This is an in-memory stand-in for the eventual Zinc-backed shared memory
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regions. The interface is explicit so the implementation can be swapped later
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without touching the kernel logic.
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"""
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from __future__ import annotations
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from dataclasses import dataclass, field
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from typing import Any, Dict, Iterable, List, Mapping, Optional, Protocol
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import threading
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import time
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from .contracts import KernelIntent, TradeSlot
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from .control import KernelControlSnapshot
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class ZincPlane(Protocol):
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"""Hot-path plane for intents, state and control."""
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def publish_intent(self, intent: KernelIntent) -> None:
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...
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def write_slot(self, slot: TradeSlot) -> None:
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...
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def read_slots(self) -> List[TradeSlot]:
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...
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def update_control(self, control: KernelControlSnapshot) -> None:
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...
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def read_control(self) -> KernelControlSnapshot:
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...
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def wait_on_intent(self, timeout_ms: int = 1000) -> bool:
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...
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def notify_intent(self) -> None:
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...
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def wait_on_state(self, timeout_ms: int = 1000) -> bool:
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...
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def notify_state(self) -> None:
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...
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def wait_on_control(self, timeout_ms: int = 1000) -> bool:
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...
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def notify_control(self) -> None:
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...
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@dataclass
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class InMemoryZincPlane:
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"""Simple in-memory Zinc lookalike for Python prototype tests."""
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intent_region: List[KernelIntent] = field(default_factory=list)
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state_region: Dict[int, TradeSlot] = field(default_factory=dict)
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control_region: Optional[KernelControlSnapshot] = None
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_intent_seq: int = field(default=0, init=False, repr=False)
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_state_seq: int = field(default=0, init=False, repr=False)
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_control_seq: int = field(default=0, init=False, repr=False)
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_intent_observed_seq: int = field(default=0, init=False, repr=False)
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_state_observed_seq: int = field(default=0, init=False, repr=False)
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_control_observed_seq: int = field(default=0, init=False, repr=False)
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_signal: threading.Condition = field(default_factory=threading.Condition, init=False, repr=False)
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def publish_intent(self, intent: KernelIntent) -> None:
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with self._signal:
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self.intent_region.append(intent)
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self._intent_seq += 1
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self._signal.notify_all()
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def write_slot(self, slot: TradeSlot) -> None:
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with self._signal:
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self.state_region[int(slot.slot_id)] = slot
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self._state_seq += 1
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self._signal.notify_all()
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def read_slots(self) -> List[TradeSlot]:
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return [self.state_region[key] for key in sorted(self.state_region)]
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def update_control(self, control: KernelControlSnapshot) -> None:
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with self._signal:
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self.control_region = control
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self._control_seq += 1
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self._signal.notify_all()
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def read_control(self) -> KernelControlSnapshot:
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if self.control_region is None:
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return KernelControlSnapshot()
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return self.control_region
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def wait_on_intent(self, timeout_ms: int = 1000) -> bool:
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return self._wait_for_change("_intent_seq", "_intent_observed_seq", timeout_ms)
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def notify_intent(self) -> None:
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with self._signal:
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self._intent_seq += 1
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self._signal.notify_all()
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def wait_on_state(self, timeout_ms: int = 1000) -> bool:
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return self._wait_for_change("_state_seq", "_state_observed_seq", timeout_ms)
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def notify_state(self) -> None:
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with self._signal:
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self._state_seq += 1
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self._signal.notify_all()
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def wait_on_control(self, timeout_ms: int = 1000) -> bool:
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return self._wait_for_change("_control_seq", "_control_observed_seq", timeout_ms)
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def notify_control(self) -> None:
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with self._signal:
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self._control_seq += 1
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self._signal.notify_all()
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def _wait_for_change(self, seq_attr: str, observed_attr: str, timeout_ms: int) -> bool:
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timeout_s = None if timeout_ms is None or timeout_ms < 0 else max(0.0, timeout_ms / 1000.0)
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deadline = None if timeout_s is None else time.monotonic() + timeout_s
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with self._signal:
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observed = getattr(self, observed_attr)
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while getattr(self, seq_attr) == observed:
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if deadline is None:
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self._signal.wait()
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continue
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remaining = deadline - time.monotonic()
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if remaining <= 0:
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return False
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self._signal.wait(timeout=remaining)
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setattr(self, observed_attr, getattr(self, seq_attr))
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return True
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